Packaging of an integrated circuit chip involves mechanical and environmental protection of the chip. Packaging further involves electrical interconnection between contacts on the chip and external electrical terminals. For example, disclosed in U.S. Pat. No. 6,777,767, which is herein incorporated by reference, is a package element separated from an integrated circuit chip by a spacer element, thereby forming a cavity. However, a top surface of the chip having the contacts of the chip faces towards the package element and the cavity. Because contacts are on the top surface of the chip, leads extend from the conductive pads around edge and bottom surfaces of the chip in order to interconnect with other entities. Despite considerable effort in the art heretofore, still further improvements would be desirable.